---

組裡招人
在台北或新竹都可以
title 範圍根據面試結果可從MTS-SMTS-PMTS
相對的薪資範圍從240-450萬(8萬-15萬美金,base salary)
RSU以及sign on bonus 另計
有興趣的請跟我聯絡 email: chihhsun@amd.com

以下是Job Description

Job Title:
        SerDes IP and System Architect, Modeling and Simulations
Job Description:
        The SerDes Architecture and Modeling Group has responsibilities in generating
robust SerDes architecture and algorithms, creating silicon and system level
specifications, developing and verifying SerDes design models, developing
IBIS-AMI models for system level simulations and for customers, evaluating
system performance margin trade-offs, analyzing system SI and PI, and
bringing up and characterizing silicon.
We’re looking for a system architect to join a fast paced transceiver design
team. Our team stays ahead of the technology curve to deliver world-class
programmable transceiver solutions for multiple FPGA platforms, supporting
over 20 protocols with thousands of customer applications.
The successful candidate will be analytical, thorough, self-driven, and have
an excellent track record in the following areas:
        ‧      Signal processing, data coding, and FEC algorithms
        ‧      SerDes architecture development including equalizers and time recovery
                for NRZ and PAM4 systems
        ‧      Behavioral modeling of different blocks in transceivers
        ‧      Familiarity with optical link analysis and evaluation is a plus
        ‧      Presenting design trade-off analyses and implementation recommendations
                with custom circuit designers

Job Requirements:
        ‧      MSEE a must and Ph.D. preferred, with minimum of 5 year working
                experience
        ‧      Signal modulation, coding, and FEC knowledge and experience
        ‧      Architecture experience with transceiver equalizers (TX FIR, RX analog
                FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred
        ‧      Architecture experience with transceiver timing recovery, such as high
                speed PLLs, CDRs, etc.
        ‧      ADC based SerDes architecture experience is a plus
        ‧      Experience with using and developing transceiver modeling, analysis,
                and characterization tools – IBIS-AMI model development experience is a plus
                and familiarity with Simulink/Matlab and C/C++ programming
        ‧      Experience with lab equipment for high-speed digital systems
        ‧      Good understanding of high speed signal integrity issues
        ‧      Excellent technical communication skills (presentations and
                documentation)
        ‧      Team player

--
※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 149.199.62.130 (美國)
※ 作者: ralphaton 2024-05-17 00:34:11
※ 文章代碼(AID): #1cHZM5Co (Tech_Job)
※ 文章網址: https://www.ptt.cc/bbs/Tech_Job/M.1715877253.A.332.html